Not applicable.
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A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever
1. Field of the Invention
The present invention generally relates to initializing a computer system. More particularly, the invention relates to simulating a xe2x80x9cmemory stackxe2x80x9d particularly when system memory is not yet available during the initialization process. More particularly still, the invention relates to the use of non-general purpose registers within a microprocessor to simulate a memory stack.
2. Background of the Invention
Each time a personal computer system is turned on, or xe2x80x9cre-bootedxe2x80x9d if already powered on, an initialization process is performed. During initialization, memory is tested and various other system components are tested and initialized. This initialization process is often referred to as the Power On Self Test (xe2x80x9cPOSTxe2x80x9d). The present invention is particularly useful during a phase of POST, although it is not limited just to the POST environment. To fully appreciate the benefits of the present invention, an understanding of a conventional computer system may be helpful.
A conventional computer system configuration is shown in FIG. 1. A central processing unit (CPU) 20, which typically includes a set of general purpose registers 22, usually couples to system memory 25 through a primary bridge and memory controller unit 30. The primary bridge and memory controller unit 30 also provides a connection to various peripheral devices (one is shown in FIG. 1) and a secondary bridge unit 35 by way of a primary peripheral bus. A non-volatile memory device 40 couples to the secondary bridge 35 through a secondary peripheral bus.
The non-volatile memory device 40 shown in FIG. 1 typically is implemented as read only memory (ROM) and contains the computer""s basic input/output system (BIOS) code. The BIOS code includes instructions that are executed by the CPU 20 to perform POST. During initialization, the CPU thus retrieves and executes POST instructions from the BIOS ROM 40 to test and initialize the computer system. The BIOS code also includes routines that are executed during normal system operation to control and access various input and output devices such as a keyboard, a floppy drive and a mouse.
One of the steps performed during POST involves testing and initializing the memory subsystem. The memory subsystem generally includes the system memory 25 and memory controller logic typically implemented as part of the primary bridge and memory controller logic 30. In most conventional computer systems available today, many devices in the computer, such as the CPU 20, can request access to the system memory 25. Because many system devices can concurrently request access to system memory 25, but only one access request generally can be processed by the memory 25 at any one point in time, a memory controller is necessary to control access to memory. The memory controller usually includes arbitration logic to determine which one request out of multiple pending memory requests will be serviced.
System memory 25 generally provides temporary xe2x80x9cscratchpadxe2x80x9d storage for data, BIOS code addresses, configuration parameters and other types of information. During initialization, the CPU 20 may store data temporarily in system memory 25 for later use in completing the initialization. Another use of system memory 25 is illustrated in FIG. 2 which shows four subroutines 50, 52, 54, and 56 that may be BIOS subroutines executed during initialization. As shown, program control can jump from one subroutine to another. For example, while executing subroutine 50, the CPU jumps to address X which begins subroutine 52. Once the CPU completes executing subroutine 52, control jumps back to subroutine 50 at return address RTNX. While executing subroutine 52, however, the CPU may also jump to address Y which begins subroutine 54. Before returning to return address RTNY at the completion of subroutine 54, the CPU may also jump to subroutine 56. After completing subroutine 56, the CPU jumps back to subroutine 54 at return address RTNZ. Thus, when program control passes to another subroutine, control must eventually return to the next sequential address following the jump instruction which initiated the change in program control.
To properly execute the subroutines, the CPU must keep track of the order in which the 20 subroutines were executed so that the CPU will return to the appropriate subroutine. The CPU generally keeps track of the order by temporarily storing the return address (RTNX, RTNY, and RTNZ in the example of FIG. 2). System memory 25 provides convenient temporary storage into which the CPU can store the return addresses. The CPU then can retrieve each return address when it is ready to jump back to a previous subroutine.
A portion of system memory 25 can be configured as a xe2x80x9cstack.xe2x80x9d A memory stack typically is a set of contiguous memory locations and includes a xe2x80x9cpointerxe2x80x9d which keeps track of the memory location in the stack with the highest memory address. That location is referred to as the xe2x80x9ctopxe2x80x9d of the stack. Each new value, such as a return address or datum, that is stored in the stack, is placed on the top of the stack. The process of storing a new value on the stack usually is referred to as xe2x80x9cpushingxe2x80x9d the value on the top of the stack. The reverse process by which the value on the top of the stack is retrieved is referred to as xe2x80x9cpoppingxe2x80x9d the value off the stack. Each time a value is pushed onto the stack, the pointer is incremented to point to the new top of stack memory location. Each time a value is popped off the stack, the pointer is decremented. As such, the current top of stack pointer value changes each time values are pushed on or popped off the stack. Data values pushed onto the stack in a particular order must be retrieved in the reverse order; that is, only the value that is stored at the current top of stack memory location can be popped off the stack.
One of the steps to be performed in initializing the memory subsystem is to test and initialize the memory controller. Until the memory controller is initialized, system memory 25 is unavailable to the rest of the computer system. As such, memory stacks cannot be configured and used until the memory controller has been initialized. The period of time during POST in which memory stacks are unavailable is referred to as a xe2x80x9cstackless environment.xe2x80x9d Alternative techniques are necessary to keep track of subroutine return addresses and to provide temporary storage of data values.
One simplistic technique is for the return addresses to be xe2x80x9chard-codedxe2x80x9d into the subroutine instructions. Using this technique, when the CPU 20 completes execution of a subroutine, control always passes to a predetermined address. This technique avoids the need to temporarily store the return addresses. This technique, however, is problematic if it is desirable to call a particular subroutine from two or more other routines. There is no mechanism to keep track of which of the two routines has called the subroutine.
Another technique has been implemented in which the return addresses are stored in the general purpose registers 22 implemented in the CPU 20 (FIG. 1). Once a return address is stored in a particular general purpose register, that particular return address subsequently can be retrieved from the register. It is important not to change contents of a general purpose register that includes a subroutine return address until the return address is retrieved. Otherwise, program control will be disrupted.
A CPU, however, only has a limited number of general purpose registers. As their name suggests, general purpose registers can be used, and typically are used, for a variety of purposes besides temporary storage of subroutine return addresses. Often, it is desirable to temporarily store a particular data value while other steps or calculations are performed by a routine. It may be desirable, for example, to temporarily store the configuration of a computer device or subsystem. Once the present configuration is saved, the CPU can change the configuration of the device or subsystem, perform a desired step, and reconfigure the device or subsystem using the previous configuration retrieved from the general purpose register.
With only a limited number of general purpose registers available in the CPU, but numerous potential uses of the registers, using the registers to store subroutine return addresses reduces the number of general purpose registers available for other uses. In the example of FIG. 2, the CPU must store three return addresses, RTNX, RTNY, and RTNZ in the general purpose registers 22. The registers that contain these three return addresses cannot be used for other purposes unit the addresses are retrieved for use. The CPU""s general purpose registers 22 represent the primary storage capability of conventional computer systems during system POST in a stackless environment.
Thus, a computer system that can make more efficient use of the CPU""s general purpose registers is needed. Such a computer system should be able to provide adequate storage for subroutine return addresses and data without compromising the availability of the CPU general purpose registers.
The deficiencies of the prior art described above are solved in large part by a computer system that simulates a memory stack in a non-general purpose register set preferably in the computer""s CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use it to store a data value for subsequent retrieval and use.
The non-general purpose register set may include memory type range registers (MTRRs) typical of certain CPU""s. One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions include instructions for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of the simulated stack.
By simulating a memory stack in non-general purpose registers, the problems described above regarding the limited availability of general purpose registers are mitigated or avoided altogether. By using non-general purpose registers to store data and return addresses, more general purpose registers are available for other uses. The various characteristics described above, as well as other features, will be readily apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments of the invention, and by referring to the accompanying drawings.